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EDGE646 Pin Electronics Driver, Window Comparator, and Switch Matrix
TEST AND MEASUREMENT PRODUCTS Description
The EDGE646 is an integrated trinary driver, window comparator, and switch matrix pin electronics solution manufactured in a wide voltage CMOS process. It is designed for automatic test equipment and instrumentation where cost, functional density, and power are all at a premium. The tristatable driver is capable of generating 3 levels one for a logic high, one for a logic low, and one for either a termination voltage or a special programming voltage. The on-board window comparator effectively determines whether the DUT is in a high, low, or intermediate state. The switches are included to allow such functions as PMU, pull up, and pull down connections.
VH VTT VL
Applications
* Low Cost Automated Test Equipment
Functional Block Diagram
The EDGE646 is intended to offer an extremely low leakage, low cost, low power, small footprint, per pin solution for 100 MHz and below pin electronics applications.
DATA DATA* DOUT DVR EN DVR EN*
VTT EN VTT EN* SW0
Features
* * * * * * * 100 MHz Operation 12V I/O Range Programmable Output Levels Flex In digital Inputs (Technology Independent) Three Level Driver Extremely Low Leakage Currents (typically ~0 nA) Small Footprint (32 Pin, 7 mm X 7 mm, TQFP Package)
SW0 EN*
SW1 SW1 EN*
LOAD
SW2
SW2 EN* VBB COMPA HIGH LEVEL VINP LOW LEVEL COMPB CVA
CVB
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EDGE646
TEST AND MEASUREMENT PRODUCTS PIN Description
Pin Name Driver DATA / DATA* DVR EN / DVR EN* VTT EN / VTT EN* DOUT VH, VL, VTT VBB Comparator VINP CVA, CVB COMPA, COMPB LOW LEVEL HIGH LEVEL Switch Matrix SW0 EN*, SW1 EN* SW2 EN* SW0 SW1 SW2 LOAD Power Supplies VCC VEE N/C 3, 22, 27 4, 21, 28 9 Positive analog power supply. Negative analog power supply. No Connect pin (leave floating). 11, 13 15 12 14 16 17 TTL compatible inputs that activate switches 0, 1, 2, and 3. Switch 0 Switch 1 Switch 2 Input pin that connects the DUT to the analog switches. 19 20, 18 5, 8 7 6 Analog window comparator input. Analog DC comparator inputs that set the threshold levels for the window comparator. Digital comparator outputs. Voltage inputs that establish the digital low and high levels of the comparator outputs. 30, 29 32, 31 2, 1 23 24, 25, 26 10 Digital input that determines the high/low status of the driver when it is enabled. Digital input that enables and disables the driver, or places the driver in the VTT state. Digital input that determines whether DVR EN* places the driver in a high impedance state or actively drives to the VTT level. Driver Output. Unbuffered analog inputs that set the voltage level of a logical 1, 0, or VTT at the driver output. Analog input pin which establishes the threshold for all singleended digital input signals. Pin # Description
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EDGE646
TEST AND MEASUREMENT PRODUCTS PIN Description (continued)
32-Pin, 7mm x 7mm TQFP
DVR EN*
DVR EN
DATA*
DATA
VCC
VEE
VTT
25 VTT EN* VTT EN VCC VEE COMPA HIGH LEVEL LOW LEVEL COMPB 9 17 1 VH DOUT VCC VEE CVA VINP CVB LOAD
VBB
SW0
SW1
SW0 EN*
SW1 EN*
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SW2 EN*
SW2
N/C
VL
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EDGE646
TEST AND MEASUREMENT PRODUCTS Circuit Description
Driver Description The EDGE646 driver supports three distinct programmable driver levels; high, low, termination, and high impedance. There are no restrictions between any of these three levels in that all three may vary independently over the entire operating voltage range between VCC and VEE. The DVR EN*, DATA, and VTT EN pins are digital inputs that control the driver (see Table 1). With DVR EN* low, DATA determines whether the driver will force VH or VL at DOUT. With DVR EN* high, VTT EN* controls whether the driver goes into high impedance or drives VTT..
DVR EN* 1 1 0 0 VTT EN 0 1 X X DATA X X 0 1 DOUT HiZ VTT VL VH
output which series terminates the transmission line to the DUT. In this environment, the driver can withstand a short to any legal DUT voltage for an indefinite period. In a low impedance application with no additional output series resistance, care must be exercised and systems should be designed to check for this condition and tristate the driver if a short is detected. The driver does NOT have on-chip short circuit protection or limitation circuitry.
VBB VBB is an analog input which establishes the threshold for all single ended digital input signals. If SW0 EN*, SW1 EN*, or SW2 EN* are more positive than VBB, these inputs are a digital "1". Conversely, if they are more negative than VBB, they are a "0". All digital inputs are wide voltage comparator inputs, so they are technology independent. By establishing the appropriate VBB level for the switch control inputs, and the appropriate differential input levels for the driver digital control inputs, the EDGE646 may be driven by TTL, ECL, CMOS, or any custom level circuitry.
SW0 EN*
Table 1. Driver Truth Table
VH, VL, and VTT VH, VL, and VTT define the logical "1", "0", and "termination" levels of the driver and can be adjusted anywhere over the range spanned by VCC to VEE. There is no restriction between VH, VL, and VTT, in that they can all vary independently over the entire voltage range determined by the power supply levels. The VH, VL, and VTT inputs are unbuffered in that they also provide the driver output current, so the sources of these voltages must have ample current drive capability. While VTT is referred to as the termination voltage, it may also be used as a very high "programming" level on many memory devices.
SW1 EN*
SW2 EN* VBB
Figure 1. Driver Digital Inputs
DATA DATA*
Driver Output Protection The EDGE646 is designed to operate in a functional testing environment where a controlled impedance (typically 50 ) is maintained between the pin electronics and the DUT. In general, there will be an external resistor at the driver
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DVR EN* DVR EN VTT EN VTT EN*
Figure 2. Driver Differential Digital Inputs
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EDGE646
TEST AND MEASUREMENT PRODUCTS Circuit Description (continued)
Receiver Functionality The EDGE646 supports an on-board window comparator. CVB and CVA are high impedance analog inputs which establish the threshold voltages. COMPA and COMPB are the digital outputs which reflect the real time status of VINP Table 2 summarizes the relationship between the . threshold levels, VINP and the output signals. ,
VINP VINP < CVA VINP > CVA VINP < CVB VINP > CVB COMPA 1 0 X X COMPB X X 0 1
Load The EDGE646 provides a total of 3 analog switches. Individual switches vary in both their on resistance and their on/off time (see Table 4). Like the driver digital inputs, the switch matrix control inputs SW0-3 EN* are technology independent as VBB determines their threshold level. The switch control is documented in Table 3.
Control Inputs SW0 EN* = 1 SW0 EN* = 0 SW1 EN* = 1 SW1 EN* = 0 SW2 EN* = 1 SW2 EN* = 0 Status SW0 disconnected SW0 connected SW1 disconnected SW1 connected SW2 disconnected SW2 connected
Table 2. Comparator Truth Table
Comparator Outputs The comparator outputs are 50 output impedance nontristatable drivers designed to cleanly drive 50 transmission lines without requiring any external series termination resistors. Input pins LOW LEVEL and HIGH LEVEL establish the logic 0 and 1 levels respectively. In normal operation, LOW LEVEL would be connected to ground and HIGH LEVEL would be connected to a system VDD supply, producing CMOS digital swings at the output. However, the comparator outputs are technology independent in that they can drive PECL, 3V CMOS, ECL, LV CMOS, GTL, and custom levels by varying LOW LEVEL and HIGH LEVEL. For example, should a 3V swing be desired, HIGH LEVEL could be connected to a 3.0V power supply. Notice that HIGH LEVEL and LOW LEVEL provide both the voltage level and the current for the comparator outputs. HIGH LEVEL and LOW LEVEL may be varied between +5V and -2V.
Table 3. Switch Matrix Truth Table
Switch SW0 SW1 SW2
Rout 50 50 50
On/Off Time 100 ns 100 ns 100 ns
Table 4. Switch Matrix Characteristics
Do NOT leave any digital input pins floating.
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EDGE646
TEST AND MEASUREMENT PRODUCTS Application Information
Power Supplies Power Supplies Decoupling
PRELIMINARY
The EDGE646 uses two power supplies for circuit opera- A .1 F capacitor is recommended between VCC and VEE. tion; VCC and VEE. In order to protect the EDGE646 and avoid damaging it, the following power supply requirements In addition, solid VCC and VEE planes are recommended must be satisifed at all times: to provide a low inductance path for the power supply currents. These planes will reduce any inductive supply VEE All Inputs VCC drops associated with swtiching currents on the power supply pins. If solid planes are not possible, then wide The sequence below can be used as a guideline when power busses are preferable. operating the EDGE646: Power-On Sequencing 1. VCC (substrate) 2. VEE 3. Inputs Power-Off Sequencing 1. Inputs 2. VEE 3. VCC VH, VL, and VTT Decoupling
As the VH, VL, and VTT inputs are unbuffered and must supply the driver output current, decoupling capacitors for these inputs are recommended in proportion to the amount The two diode configuration shown in Figure 3 should be of output current the application requires. In general, a used on a once-per-board basis to ensure power supply surge current of 50 mA (5V swings series terminated with sequence and fault tolerance. 50 Ohms into a 50 Ohm transmission line) are the maximum dynamic output currents the driver should see. The VCC decoupling capacitors should be able to provide this current for the duration of the round trip time between the pin electronics and the DUT, and then recharge themselves before the next such transition would occur. Once this condition is satisfied, the VH, VL, and VTT supply voltages 1N5820 or are more responsible for establishing the DC levels assoEquivalent ciated with each function and recharging the capacitors, rather than providing the actual dynamic currents required to drive the DUT transmission line.
VEE
Ideally, VH, VL, and VTT would each have a dedicated power layer on the PC board for the lowest possible inductance power supply distribution.
Figure 3. Power Supply Protection Scheme Warning: It is extremely important that the voltage on any device pin does not exceed the range of VEE -0.5V to VCC +0.5V at any time, either during power up, normal operation, or during power down. Failure to adhere to this requirement could result in latchup of the device, which could be destructive if the system power supplies are capable of supplying large amounts of current. Even if the device is not immediately destroyed, the cumulative damage caused by the stress of repeated latchup may affect device reliability.
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EDGE646
TEST AND MEASUREMENT PRODUCTS Package Information
TOP VIEW
PRELIMINARY
PIN Descriptions
4 D
D/2
3 e
b E 4
N / 4 TIPS 0.20 C 4X A-B D
E/2 SEE DETAIL "A"
BOTTOM VIEW
5 D1
7
D1 / 2
E1 / 2
5
7
E1
C
OO
4X
0.20
H
A-B
D
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EDGE646
TEST AND MEASUREMENT PRODUCTS Package Information (continued)
DETAIL "A"
DETAIL "B"
0 MIN.
3 e/2
- 0.05 S A1 DATUM PLANE -H- 0.08 / 0.20 R. 0.25 GAUGE PLANE
A2
C.08 R. MIN. 0.20 MIN. L 1.00 REF.
0-7
b
SECTION C-C
8 PLACES 11 / 13
A
0.05
-H-
2
//
0.10 C 0.09 / 0.20
ccc -C- M SEE DETAIL "B"
;;; ;;;
9 ddd b b 1
M C A-B S
DS
WITH LEAD FINISH
0.09 / 0.16
Lead Cross Section
BASE METAL
Notes: 1. All dimensions and tolerances conform to ANSI Y14.5-1982. 2. Datum plane -H- located at mold parting line and coincident with lead, where lead exits plastic body at bottom of parting line. 3. Datums A-B and -D- to be determined at centerline between leads where leads exit plastic body at datum plane -H-. 4. To be determined at seating plane -C-. 5. Dimensions D1 and E1 do not include mold protrusion. 6. "N" is the total # of terminals. 7. These dimensions to be determined at the datum plane -H-. 8. Package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package. 9. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius or the foot. 10. Controlling dimension: millimeter. 11. Maximum allowable die thickness to be assembled in this package family is 0.30 millimeters. 12. This outline conforms to JEDEC publication 95, registration MO-136, variations AC, AE, and AF.
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A A1 A2 D D1 E E1 L M N e b b1 ccc ddd
JEDEC VARIATION All Dimensions in Millimeters AC Min. Nom. Max. Note 1.60 0.05 0.10 0.15 1.35 1.40 1.45 9.00 BSC. 4 7.00 BSC. 7,8 9.00 BSC. 4 7.00 BSC. 7,8 0.45 0.60 0.75 0.15 32 0.80 BSC. 0.30 0.37 0.45 9 0.30 0.35 0.40 0.10 0.20
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EDGE646
TEST AND MEASUREMENT PRODUCTS Recommended Operating Conditions
Parameter Positive Analog Power Supply Negative Analog Power Supply Total Analog Power Supply Comparator Output High Level Comparator Output Low Level Junction Temperature Symbol VCC VEE VCC - VEE HIGH LEVEL LOW LEVEL TJ Min 6 -5 9 -2 -2 Typ 8 -4 Max 12 -3 12 +5 +5 +125 Units V V V V V
oC
Absolute Maximum Ratings
Parameter Total Analog Power Supply Positive Analog Power Supply Negative Analog Power Supply Analog Input Voltages Digital Inputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature TJ TA Symbol VCC - VEE VCC VEE Min 0 0 -6 VEE - .5 VEE - .5 -55 -65 Typ Max 13 13 0 VCC + .5 VCC + .5 +125 +150 +150 260 Units V V V V V
oC oC oC oC
Stresses above listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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EDGE646
TEST AND MEASUREMENT PRODUCTS DC Characteristics
Driver/Receiver Characteristics
Parameter Driver Programmable Driver Output Voltages Driver Output Swing VH, VL, VTT VH - VL VH - VTT VTT - VLL Iout DC Iout AC Rout Cout Ileak VEE VEE - VCC VEE - VCC VEE - VCC -50 -220 20 25 13 0 4 VCC VCC - VEE VCC - VEE VCC - VEE +50 +220 32 V V V V mA mA pF nA Symbol Min Typ Max Units
DC Driver Output Current AC Driver Output Current (Note 1) Output Impedance DUT Pin Capacitance (Note 1) HiZ Leakage Current (Notes 1, 2) Comparator Input Voltage Input Leakage Current (Notes 1, 2) Input Capacitance (Note 1) Offset Voltage (Note 3) Receiver Threshold (Note 3) Threshold Bias Current (Note 1) Digital Output High Level Digital Outptu Low Level Digital Output Impedance (Note 4) Digital Output Current Drive Analog Switches (SW0, SW1, SW2) On Resistance Voltage Range LOAD HiZ Leakage Current (Notes 1, 2) DC Current Rating SW Capacitance Total Power Supply Quiescent Positive Supply Current Quiescent Negative Supply Current Total Leakage (Note 1) (DOUT + VINP + LOAD) Total Capacitance (Note 1) (DOUT + VINP + LOAD)
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VINP IBIAS Cin VOS
VEE 0 4 0 VEE + 3.0
VCC 2
V nA pF
+200 VCC - 2.0 0 10 5 5 37 45 +50
mV V nA V V mA
CVA, CVB HIGH LEVEL LOW LEVEL Rout Imax -2 -2 31 -50
Ron
30 VEE
36
44 VCC
V nA mA pF
0 -30 10
4 +30
ICC_DC IEE_DC
30 30
mA mA
0 27
10
10
nA pF
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EDGE646
TEST AND MEASUREMENT PRODUCTS DC Characteristics (continued)
Digital Inputs DATA / DATA*, DVR EN* / DVR EN, VTT EN / VTT EN* SW0 EN*, SW1 EN*, SW2 EN*
Parameter Input High Voltage Input Low Voltage Input Current Input Capacitance
Symbol Input - Input* Input* - Input IIN DATA DRV EN VTT EN INPUT, INPUT* VBB
Min .8 .8
Typ
Max 5 5
Units V V A pF pF pF V V
0
1.0 8 8 8
Digital Input Voltage Range Digital Input Threshold
-2.0* -1.4
+5.0 4.4
*-2V or (VEE + 2.0V), whichever is more positive. Note Note Note Note 1: 2: 3: 4: This parameter is guaranteed by design and characterization. Production testing is performed against a 250 nA limit. Measured at 0V. Measured at HIGH LEVEL = +3V, LOW LEVEL = 0V.
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EDGE646
TEST AND MEASUREMENT PRODUCTS AC Characteristics
Parameter Driver P ropag at ion Delay ( Not e 3) DA T A I N t o DOUT V T T EN t o DOUT DV R EN* t o DOUT ( A c t iv e t o HiZ ) ( Not e 5) DV R EN* t o DOUT ( HiZ t o A c t iv e) ( Not e 5) DA T A t o V T T P rop Delay M at c hing ( Not e 4) M inimum P ulse W idt h ( 3V Sw ing ) T og g le R at e ( Not e 6) DOUT Out put R ise/ F all T imes ( Not es 1, 4) 1V Sw ing ( 20% - 80%) 3V Sw ing ( 10% - 90%) 5V Sw ing ( 10% - 905) Comparator C omparat or Dig it al Out put s ( Not es 2, 4) R ise T ime ( 10% - 90%) F all t ime ( 10% - 90%) V I NP t o C OM P A , C OM P B M inimum P ulse W idt h T og g le R at e ( Not e 6) T pd v s. Ov erdriv e 400 mV Ov erdriv e 200 mV Ov erdriv e T pd R ise, T pd F all Errors Sw it c h M at rix SW 0, 1, 2 EN* t o Sw it c h On/ Off 10 20 F max 100 3.0 5.0 2.0 50 tr tf T pd 1.5 1.5 8 4 2.5 2.5 11 5 ns ns ns ns M Hz ns ns ns ns F max 100 1.2 1.5 2.0 1.6 2.0 3.5 7 7 7 7 -1.2 11 11 11 11 14 14 14 14 1.2 5 ns ns ns ns ns ns M Hz
ns ns ns
Symbol
Min
Typ
Max
Units
4
1.0
4
Note 1: Note Note Note Note Note 2: 3: 4: 5: 6:
Into 1M of 50 transmission line terminated with 1K and 5 pF with the proper series termination resistor. LOW LEVEL = 0V, HIGH LEVEL = 3.3V. Measured at 2.5V with VH = +5V, VL = 0V. Guaranteed by design and characterization. This parameter is not tested in production. Tested with a 30 mA load. Guaranteed by characterization. (This parameter is tested in production against 40 MHz limits.)
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EDGE646
TEST AND MEASUREMENT PRODUCTS Ordering Information
Model Number E646ATF EVM646ATF
Package 32-Pin TQFP EDGE646 Evaluation Module
Contact Information
Semtech Corporation Test and Measurement Division 10021 Willow Creek Rd., San Diego, CA 92131 Phone: (858)695-1801 FAX (858)695-2633
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EDGE646
TEST AND MEASUREMENT PRODUCTS Revision History
Current Revision Date: October 21, 2002 Previous Revision Date: October 27, 2000
Page # 6
Section Name Latchup Protection
Previous Revision
Current Revision Change Section name to "Power Supplies" Update section.
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